The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work, is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, is neither expressly nor impliedly admitted as prior art against the present disclosure.
Data error rates in traditional flash memory devices depend on, the duration of time that the flash memory devices operate, the duration of time the data is retained in the memory, as well as the number of program-erase (PE) cycles of the page where the data resides and many other factors. For example, as the flash memory device operates, the reliability of the raw flash memory degrades significantly. In particular, raw bit error rates (BER) and signal to noise ratios (SNR) become worse during normal PE cycles and data retention duration decreases. In order to satisfy rigorous reliability requirements for data storage applications, a storage controller may be responsible for maintaining, throughout, the use of a storage device and regardless of the actual BER, similar or consistent corrected bit error rates (CBER), which are the error rates perceived by a user.
Traditional storage applications use error correction code circuitries (ECC) to encode stored data and decoding engines to detect/correct data errors encountered when reading the data from the flash memory storage devices. A storage application may employ increasingly stronger error correction encoding and decoding techniques in order to maintain similar or consistent CBER. For example, a storage application and/or a storage controller may employ low-density parity check (LDPC) coding techniques to achieve these goals. Such LDPC coding techniques involve the use of soft iterative decoding techniques, which involve the decoder making several iterations to decode stored encoded information. As used herein, encoded information can be grouped into units called “codewords.” Codewords may contain “symbols,” which are groupings of one or more bits.
Soft iterative decoding uses soft data associated with a stored codeword to decode the codeword. As used herein, soft data or information is data that indicate the probability that a symbol in the codeword is a particular data symbol, such as “0” or “1” in a binary system. In contrast to soft iterative decoding, hard decision decoding (equivalently hard data decoding) is based on hard data (i.e., hard decisions) associated with the stored, codeword. As used herein, hard, data, hard decisions consist of data corresponding to the original codeword symbols.
When traditional flash memory storage systems employ soft iterative decodable codes for storage applications, the complexity of the decoder may become substantially higher than when, for example, algebraic codes (such as BCH codes or Reed-Solomon codes) that require hard decision decoding using hard data. In addition when traditional flash memory storage systems employ soft iterative decodable codes for storage applications, the acquisition of soft data input (soft data about the stored codewords to be decoded) may be difficult to obtain (i.e., the soft, data may require a substantially long period of time to obtain and/or may consume a lot of power to obtain). This is because most flash storage is optimized to output hard decisions rather than soft data. Because of these difficulties in employing soft iterative decodable codes, the implementation of such codes for flash memory storage applications may not be highly desired due to the increased power usage and decreased throughput that may result in decoding such codes.